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Ultra-dense nano- and molecular-electronic circuits

Citation

Green, Jonathan Earl (2007) Ultra-dense nano- and molecular-electronic circuits. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-05312007-142846

Abstract

This thesis describes research towards the realization of large-scale, ultra-dense nanowire-based circuits. The primary means for the construction of such circuits is the superlattice nanowire pattern transfer (SNAP) technique. This technique was optimized for the fabrication of large nanowire arrays containing over 1000 nanowires at narrow pitch and aligned over millimeter length scales. Silicon nanowire arrays were fabricated with wire widths down to ten nanometers, and with precisely-controlled electronic properties and bulk-like resistivity values through the use of diffusion doping and the selection of high-quality silicon-on-insulator substrates.

A binary tree demultiplexer circuit allows the unique addressing of N nanowires from within an ultra-dense array using of order 2xlog2(N) control wires. An implementation of this circuit was experimentally demonstrated to bridge from the submicrometer dimensions of lithographic patterning to the nanometer-scale dimensions of SNAP patterning. This circuit utilized field-effect gating by relatively large control wires to address individual nanowires from within a 150-nanowire array patterned at a wire width and pitch of 13 and 34 nanometers, respectively.

Silicon- and metal-nanowire arrays were integrated with [2]rotaxane molecular materials for the fabrication of an ultra-dense, 160,000-bit crosspoint molecular electronic memory circuit. This circuit is patterned at a record density of 1x10^11 bits per square centimeter (device-pitch of 33 nanometers), and contains bistable, electrochemically addressable [2]rotaxane switching molecules as the data storage elements within the individual crosspoint junctions. Defective junctions could be readily identified through electronic testing and isolated through software coding. The working bits could then be configured to form a functional memory circuit. The molecular-mechanical nature of the switching mechanism was confirmed through volatility measurements.

An optimized two-step chlorination/methylation protocol was used to methyl passivate thin (~20-nanometer) silicon(111)-on-insulator microelectronic device surfaces, that were then demonstrated to be stable in air for arbitrarily long periods, and to resist oxidation due to common microelectronic fabrication procedures and wet-chemical treatments. Additionally, temperature-dependent mobility data showed that methylated silicon-on-insulator surfaces can be prepared with bulk-like mobility characteristics through careful optimization of the methylation reaction protocol.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:crossbar architecture; defect tolerance; high density computer memory; nanoelectronics; nanofabrication; nanotechnology; silicon interface; SOI; surface passivation
Degree Grantor:California Institute of Technology
Division:Chemistry and Chemical Engineering
Major Option:Chemistry
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Heath, James R.
Thesis Committee:
  • Goddard, William A., III (chair)
  • Heath, James R.
  • Okumura, Mitchio
  • Lewis, Nathan Saul
Defense Date:18 May 2007
Author Email:jegreen (AT) caltech.edu
Record Number:CaltechETD:etd-05312007-142846
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-05312007-142846
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:2341
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:01 Jun 2007
Last Modified:26 Dec 2012 02:50

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