Browse by Advisor

2013

DeLorimier, Michael John (2013) GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/M3TW-7Y53. https://resolver.caltech.edu/CaltechTHESIS:08192012-145253489

Mehta, Nikil (2013) An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/358S-CW22. https://resolver.caltech.edu/CaltechTHESIS:10072012-230900231

2011

Kapre, Nachiket Ganesh (2011) SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/QVZR-VB52. https://resolver.caltech.edu/CaltechTHESIS:10262010-082537998

2010

Gojman, Benjamin (2010) Algorithms and Techniques for Conquering Extreme Physical Variation in Bottom-Up Nanoscale Systems. Master's thesis, California Institute of Technology. doi:10.7907/BBC7-XK34. https://resolver.caltech.edu/CaltechTHESIS:04052010-152122284

2008

Naeimi, Helia (2008) Reliable Integration of Terascale Systems with Nanoscale Devices. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/P842-7B49. https://resolver.caltech.edu/CaltechETD:etd-01242008-012650

2006

Kapre, Nachiket Ganesh (2006) Packet-Switched On-Chip FPGA Overlay Networks. Master's thesis, California Institute of Technology. doi:10.7907/8NFZ-4Y29. https://resolver.caltech.edu/CaltechETD:etd-05312006-164059

Mehta, Nikil (2006) Time-Multiplexed FPGA Overlay Networks on Chip. Master's thesis, California Institute of Technology. doi:10.7907/WZTS-XR26. https://resolver.caltech.edu/CaltechETD:etd-05312006-164103

2005

Naeimi, Helia (2005) A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design. Master's thesis, California Institute of Technology. doi:10.7907/Z5AS-8A57. https://resolver.caltech.edu/CaltechETD:etd-05052005-164226

deLorimier, Michael John (2005) Floating-Point Sparse Matrix-Vector Multiply for FPGAs. Master's thesis, California Institute of Technology. doi:10.7907/FCCD-FA51. https://resolver.caltech.edu/CaltechETD:etd-05132005-144347