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Packet-switched on-chip FPGA overlay networks


Kapre, Nachiket Ganesh (2006) Packet-switched on-chip FPGA overlay networks. Master's thesis, California Institute of Technology.


As we scale to larger chip capacities, it becomes possible to map large, concurrent applications to programmable fabrics. These applications often have irregular and dynamic communication requirements. Packet-switched networks provide efficient implementations for such applications on these fabrics. In this research, we show how to engineer high-performance packet-switched on-chip networks and provide quantitative comparisons between different kinds of these networks. We analyse different network topologies and justify selection of topologies based on experimental results. We investigate packet-switched and time-multiplexed styles of routing and provide guidance on which style is appropriate for which application.

Item Type:Thesis (Master's thesis)
Subject Keywords:adaptive routing; BFT; butterfly fat tree; cut-through; fpga; network on chip; networks; NoC; on-chip; packet switched; packet switching; virtual channels
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • DeHon, Andre
Thesis Committee:
  • Unknown, Unknown
Defense Date:31 May 2006
Non-Caltech Author Email:nachiket (AT)
Record Number:CaltechETD:etd-05312006-164059
Persistent URL:
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:2334
Deposited By: Imported from ETD-db
Deposited On:05 Jun 2006
Last Modified:26 Dec 2012 02:50

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