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Algorithms and Techniques for Conquering Extreme Physical Variation in Bottom-Up Nanoscale Systems


Gojman, Benjamin (2010) Algorithms and Techniques for Conquering Extreme Physical Variation in Bottom-Up Nanoscale Systems. Master's thesis, California Institute of Technology. doi:10.7907/BBC7-XK34.


Nanowire building blocks provide a promising path to small feature size and thus the ability to more densely pack logic. However, the small feature size and novel, bottom-up manufacturing process will exhibit extreme variation and produce many devices that operate outside acceptable operating ranges. One-mapping-fits-all, prefabrication assignment of logical functions to physical transistors that exhibit high threshold variation will not work—combining the wide range of physical variation in transistor threshold voltage with the wide range of fanouts in the design produces an unworkably large composite range of possible delays. Nonetheless, by carefully matching the fanout of each net to the physical threshold voltages of devices after fabrication, it is possible to reduce the net range of path delays sufficiently to achieve high system yield. Characterization of the complete threshold voltage distribution present in the system can be measured at a rate of 108 resources per second by augmenting the system with voltage comparison mechanisms. By adding a modest amount of extra resources, we achieve 100% yield for systems built out of devices with 38% variation, the ITRS prediction for threshold variation in 5 nm transistors. Moreover, for these systems, we maintain delay, energy and area close to the variation-free nominal case. What’s more, there is only a 10% overhead when the measurement precision is limited to ten discrete threshold voltage values.

Item Type:Thesis (Master's thesis)
Subject Keywords:CAD Algorithms; Measurement Techniques; Measurement Precision; Nanoscale Systems; Reconfigurable Logic; Extreme Variation, Sublithographic Systems; Stochastic Variation; Logical Variation; Physical Variation; Matching; Reconfigurable Circuits; FPGA; NanoPLA; Nanowires; Routing; Placement; Mapping; Defect Tolerance; Variation Tolerance; Greedy Algorithms; EDA
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Desbrun, Mathieu (advisor)
  • DeHon, Andre (co-advisor)
Thesis Committee:
  • None, None
Defense Date:5 April 2010
Funding AgencyGrant Number
NSF CCF-0904577
Record Number:CaltechTHESIS:04052010-152122284
Persistent URL:
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:5690
Deposited By: Benjamin Gojman
Deposited On:09 Apr 2010 21:53
Last Modified:08 Nov 2019 18:08

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