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NNumber of items: 9.
D
deLorimier, Michael John
(2013)
GRAph parallel actor language : a programming language for parallel graph algorithms.
Dissertation (Ph.D.), California Institute of Technology.
http://resolver.caltech.edu/CaltechTHESIS:08192012-145253489
deLorimier, Michael
(2006)
Floating-point sparse matrix-vector multiply for FPGAs.
Master's thesis, California Institute of Technology.
http://resolver.caltech.edu/CaltechETD:etd-05132005-144347
G
Gojman, Benjamin
(2010)
Algorithms and techniques for conquering extreme physical variation in bottom-up nanoscale systems.
Master's thesis, California Institute of Technology.
http://resolver.caltech.edu/CaltechTHESIS:04052010-152122284
K
Kapre, Nachiket Ganesh
(2010)
SPICE2 -- a spatial parallel architecture for accelerating the spice circuit simulator.
Dissertation (Ph.D.), California Institute of Technology.
http://resolver.caltech.edu/CaltechTHESIS:10262010-082537998
Kapre, Nachiket Ganesh
(2006)
Packet-switched on-chip FPGA overlay networks.
Master's thesis, California Institute of Technology.
http://resolver.caltech.edu/CaltechETD:etd-05312006-164059
M
Mehta, Nikil
(2013)
An ultra-low-energy, variation-tolerant FPGA architecture using component-specific mapping.
Dissertation (Ph.D.), California Institute of Technology.
http://resolver.caltech.edu/CaltechTHESIS:10072012-230900231
Mehta, Nikil
(2006)
Time-multiplexed FPGA overlay networks on chip.
Master's thesis, California Institute of Technology.
http://resolver.caltech.edu/CaltechETD:etd-05312006-164103
N
Naeimi, Helia
(2008)
Reliable integration of terascale systems with nanoscale devices.
Dissertation (Ph.D.), California Institute of Technology.
http://resolver.caltech.edu/CaltechETD:etd-01242008-012650
Naeimi, Helia
(2005)
A greedy algorithm for tolerating defective crosspoints in nanoPLA design.
Master's thesis, California Institute of Technology.
http://resolver.caltech.edu/CaltechETD:etd-05052005-164226
This list was generated on Fri May 24 02:31:06 2013 PDT.
