HEX: A Hierarchical Circuit Extractor

Citation

Oyang, Yen-Jen (1984) HEX: A Hierarchical Circuit Extractor. Master's thesis, California Institute of Technology. doi:10.7907/mptd-b683. https://resolver.caltech.edu/CaltechTHESIS:05022012-105611552

Abstract

This report describes the algorithm, implementation, and performance of a hierarchical circuit extractor, HEX, for Metal-Oxide Semiconductor (MOS) layout designs at Caltech. The input to HEX is a layout design in Caltech Intermediate Form (CIF), a hierarchical layout description language, and the output is a hierarchical netlist describing the circuit. HEX avoids redundant work by finding out the repetitive cells in the input CIF file. To handle overlapping instances, HEX modifies the hierarchy in the CIF file to generate a new one without overlapping instances. HEX then traverses the resulting hierarchical structure, calls a flat extractor to extract leaf cells and composes cells bottom up to get the circuit information of the whole chip.

Item Type:

Thesis (Master's thesis)

Subject Keywords:

Computer Science

Degree Grantor:

California Institute of Technology

Division:

Engineering and Applied Science

Major Option:

Computer Science

Thesis Availability:

Public (worldwide access)

Research Advisor(s):

Bryant, Randy

Thesis Committee:

Unknown, Unknown

Defense Date:

1 June 1984

Other Numbering System:

Other Numbering System Name	Other Numbering System ID
UNSPECIFIED	5139-TR-84

Record Number:

CaltechTHESIS:05022012-105611552

Persistent URL:

https://resolver.caltech.edu/CaltechTHESIS:05022012-105611552

DOI:

10.7907/mptd-b683

Default Usage Policy:

No commercial reproduction, distribution, display or performance rights in this work are provided.

ID Code:

7000

Collection:

CaltechTHESIS

Deposited By:

Benjamin Perez

Deposited On:

02 May 2012 18:11

Last Modified:

09 Nov 2022 19:20

Thesis Files

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