FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems

Citation

Ng, Charles H. (1982) FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems. Master's thesis, California Institute of Technology. doi:10.7907/vdzd-7h35. https://resolver.caltech.edu/CaltechTHESIS:04132012-082850723

Abstract

This thesis describes a family of VLSI chips designed to link a number of processors on a one-to-one basis. With these chips as communication system building blocks, a complex multiprocessor system can be built. Inter-processor communication within the multiprocessor system is accomplished by passing messages composed of data packets.

The resulting chip, called a First-in-first-out Buffering Transceiver (FIBT), provides a full duplex communication channel between any two processors. FIFO queues are provided for buffering data on each communication channel. FIBT accepts data packets from the host processor via a parallel data bus and serially sends them out to the destined processor. FIBT handshakes with the processor by using asynchronous interrupt signals.

Linkage between any two FIBTs is accomplished by using only two wires. Both data bits and handshaking signals are sent by these two lines. The FIBT system is neither a synchronous nor an asynchronous one; instead, it is an "one-clock-different-phases" system. A clock signal sets up the frequency reference; the start and stop bits set up the phase reference.

Finally, FIBT is implemented in nMOS technology. The design of the circuit is discussed in detail. The design is generalized enough so that data packets of various sizes can be handled. The layout of the chip is coded in an integrated circuit descriptive language. Any member of the family of chips can be obtained by changing three basic parameters. Techniques used in verifying the circuit are shown, and several observations about VLSI design are offered.

Thesis Files