Parallel Analog Computation with Charge Coupled Devices

Citation

Neugebauer, Charles F. (1993) Parallel Analog Computation with Charge Coupled Devices. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/3e7h-9p50. https://resolver.caltech.edu/CaltechETD:etd-08312007-094832

Abstract

Many signal processing and neural network algorithms can be mathematically described in terms of vector matrix multiplication. This thesis introduces two new architectures for computing high-speed vector matrix multiplication using charge coupled devices. These integrated circuits have been designed to accept optical matrix input as well as direct electrical matrix input. In both architectures, the matrix elements are stored as analog charge packets in CCD wells while the vectors are communicated to and from the integrated circuits by electrical means. The first architecture accomplishes the vector matrix product using a semiparallel computation scheme that requires N clock cycles of the device to complete one vector matrix multiplication where N is the length of the input vector. An analysis of the linearity and charge transfer induced errors is given. The circuit represents an advance over other analog signal processors in density and speed but has serious shortcomings in accuracy, particularly the limited precision of the input vectors. The second architecture is based on charge injection device (CID) imager arrays and addresses many of the inadequacies of the semiparallel architecture. A fully parallel circuit, the CID has similar density and much higher computation speed and accuracy. A novel digital input method is introduced that extends the input vector precision significantly. In addition, accuracy issues related to charge transfer efficiency are resolved. An analysis of linearity and accuracy is provided showing the advantages of the architecture over previous implementations.

Thesis Files