Packet-Switched On-Chip FPGA Overlay Networks

Citation

Kapre, Nachiket Ganesh (2006) Packet-Switched On-Chip FPGA Overlay Networks. Master's thesis, California Institute of Technology. doi:10.7907/8NFZ-4Y29. https://resolver.caltech.edu/CaltechETD:etd-05312006-164059

Abstract

As we scale to larger chip capacities, it becomes possible to map large, concurrent applications to programmable fabrics. These applications often have irregular and dynamic communication requirements. Packet-switched networks provide efficient implementations for such applications on these fabrics. In this research, we show how to engineer high-performance packet-switched on-chip networks and provide quantitative comparisons between different kinds of these networks. We analyse different network topologies and justify selection of topologies based on experimental results. We investigate packet-switched and time-multiplexed styles of routing and provide guidance on which style is appropriate for which application.

Thesis Files