Ng, Charles H. (1982) FIFO Buffering Transceiver: A Communication Chip Set for Multiprocessor Systems. Master's thesis, California Institute of Technology. http://resolver.caltech.edu/CaltechTHESIS:04132012-082850723
This thesis describes a family of VLSI chips designed to link a number of processors on a one-to-one basis. With these chips as communication system building blocks, a complex multiprocessor system can be built. Inter-processor communication within the multiprocessor system is accomplished by passing messages composed of data packets.
The resulting chip, called a First-in-first-out Buffering Transceiver (FIBT), provides a full duplex communication channel between any two processors. FIFO queues are provided for buffering data on each communication channel. FIBT accepts data packets from the host processor via a parallel data bus and serially sends them out to the destined processor. FIBT handshakes with the processor by using asynchronous interrupt signals.
Linkage between any two FIBTs is accomplished by using only two wires. Both data bits and handshaking signals are sent by these two lines. The FIBT system is neither a synchronous nor an asynchronous one; instead, it is an "one-clock-different-phases" system. A clock signal sets up the frequency reference; the start and stop bits set up the phase reference.
Finally, FIBT is implemented in nMOS technology. The design of the circuit is discussed in detail. The design is generalized enough so that data packets of various sizes can be handled. The layout of the chip is coded in an integrated circuit descriptive language. Any member of the family of chips can be obtained by changing three basic parameters. Techniques used in verifying the circuit are shown, and several observations about VLSI design are offered.
|Item Type:||Thesis (Master's thesis)|
|Subject Keywords:||Computer Science|
|Degree Grantor:||California Institute of Technology|
|Division:||Engineering and Applied Science|
|Major Option:||Computer Science|
|Thesis Availability:||Restricted to Caltech community only|
|Defense Date:||1 December 1982|
|Other Numbering System:|
|Default Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Benjamin Perez|
|Deposited On:||13 Apr 2012 16:12|
|Last Modified:||26 Dec 2012 04:41|
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