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RTsim: A register transfer simulator

Citation

Lam, Jimmy (1983) RTsim: A register transfer simulator. Master's thesis, California Institute of Technology. http://resolver.caltech.edu/CaltechTHESIS:04112012-091046970

Abstract

The growing complexity and size of VLSI processors are demanding extremely accurate, simulation facilities for microcode debugging, logic verification, and system integration. However, reliance on mask iterations to remedy problems on a chip not only raises costs, but also extends the design cycle. Simulation justifies itself in both the turn around time and the design cost. Gate level simulation is one method for reducing errors in a chip design. However, gate level simulation of large designs are extremely expensive, and sometimes impossible when the gate level representation is not known. This thesis attempts to solve this problem by providing a functional modeling language, a reconfigurable assembler, and a functional simulation program. Mixed-level simulation capability is also provided by allowing the replacement of a functional unit by a transistor network which is being simulated by a switch-level logic simulator.

Item Type:Thesis (Master's thesis)
Subject Keywords:Computer Science
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Restricted to Caltech community only
Research Advisor(s):
  • Bryant, Randy
Thesis Committee:
  • Unknown, Unknown
Defense Date:1 April 1983
Other Numbering System:
Other Numbering System NameOther Numbering System ID
UNSPECIFIED5081:TR:83
Record Number:CaltechTHESIS:04112012-091046970
Persistent URL:http://resolver.caltech.edu/CaltechTHESIS:04112012-091046970
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:6905
Collection:CaltechTHESIS
Deposited By: Benjamin Perez
Deposited On:11 Apr 2012 16:48
Last Modified:26 Dec 2012 04:41

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