CaltechTHESIS
  A Caltech Library Service

High-performance silicon nanowire electronics

Citation

Huang, Ruo-Gu (2012) High-performance silicon nanowire electronics. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechTHESIS:12142011-124639130

Abstract

This thesis explores 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications via the fabrication and testing of SiNW-based ring oscillators. Both SiNW surface treatments and dielectric annealing are reported for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV), high carrier mobilities (~269 cm2/V•s), and low subthreshold swing (~80 mV/dec). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs is explored as well. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.

A set of novel charge-trap non-volatile memory devices based on high-performance SiNW FETs are well investigated. These memory devices integrate Fe2O3 quantum dots (FeO QDs) as charge storage elements. A template-assisted assembly technique is used to align FeO QDs into a close-packed, ordered matrix within the trenches that separate highly aligned SiNWs, and thus store injected charges. A Fowler-Nordheim tunneling mechanism describes both the program and erase operations. The memory prototype demonstrates promising characteristics in terms of large threshold voltage shift (~1.3 V) and long data retention time (~3 × 106 s), and also allows for key components to be systematically varied. For example, varying the size of the QDs indicates that larger diameter QDs exhibit a larger memory window, suggesting the QD charging energy plays an important role in the carrier transport. The device temperature characteristics reveal an optimal window for device performance between 275K and 350K.

The flexibility of integrating the charge-trap memory devices with the SiNW logic devices offers a low-cost embedded non-volatile memory solution. A building block for a SiNW-based field-programmable gate array (FPGA) is proposed in the future work.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:Silicon nanowire, ring oscillator, charge-trap memory, quantum dot, asynchronous logic
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Electrical Engineering
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Heath, James R.
Thesis Committee:
  • Heath, James R. (chair)
  • Yariv, Amnon
  • Scherer, Axel
  • Schwab, Keith C.
  • Greer, Julia R.
Defense Date:6 December 2011
Record Number:CaltechTHESIS:12142011-124639130
Persistent URL:http://resolver.caltech.edu/CaltechTHESIS:12142011-124639130
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1007/s12274-011-0157-2DOIUNSPECIFIED
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:6750
Collection:CaltechTHESIS
Deposited By: Ruo-gu Huang
Deposited On:06 Jan 2012 22:44
Last Modified:26 Dec 2012 04:39

Thesis Files

[img]
Preview
PDF (Ruo-Gu Huang's Ph.D. thesis) - Final Version
See Usage Policy.

3169Kb

Repository Staff Only: item control page