Citation
Pénzes, Paul Ivan (2002) Energydelay complexity of asynchronous circuits. Dissertation (Ph.D.), California Institute of Technology. https://resolver.caltech.edu/CaltechTHESIS:03022011131111881
Abstract
In this thesis, a circuitlevel theory of energydelay complexity is developed for asynchronous circuits. The energydelay efficiency of a circuit is characterized using the metric Et^n , where E is the energy consumed by the computation, t is the delay of the computation, and n is a positive number that reflects a chosen tradeoff between energy and delay. Based on theoretical and experimental evidence, it is argued that for a circuit optimized for minimal Et^n, the consumed energy is independent, in first approximation, of the types of gates (NAND, NOR, etc.) used by the circuit and is solely dependent on n and the total amount of wiring capacitance switched during computation. Conversely, the circuit speed is independent, in first approximation, of the wiring capacitance and depends only on n and the types of gates used. The complexity model allows us to compare the energydelay efficiency of two circuits implementing the same computation. On the other hand, the complexity model itself does not say much about the actual transistor sizes that achieve the optimum. For this reason, the problem of transistor sizing of circuits optimized for Et^n is investigated, as well. A set of analytical formulas that closely approximate the optimal transistor sizes are explored. An efficient iteration procedure that can further improve the original analytical solution is then studied. Based on these results, a novel transistorsizing algorithm for energydelay efficiency is introduced. It is shown that the Et^n metric for the energydelay efficiency index n ≥ 0 characterizes any optimal tradeoff between the energy and the delay of a computation. For example, any problem of minimizing the energy of a system for a given target delay can be restated as minimizing Et^n for a certain n. The notion of minimumenergy function is developed and applied to the parallel and sequential composition of circuits in general and, in particular, to circuits optimized through transistor sizing and voltage scaling. Bounds on the energy and delay of the optimized circuits are computed, and necessary and sufficient conditions are given under which these bounds are reached. Necessary and sufficient conditions are also given under which components of a design can be optimized independently so as to yield a global optimum when composed. Through these applications, the utility of the minimumenergy function is demonstrated. The use of this minimumenergy function yields practical insight into ways of improving the overall energydelay efficiency of circuits.
Item Type:  Thesis (Dissertation (Ph.D.)) 

Subject Keywords:  Computer Science 
Degree Grantor:  California Institute of Technology 
Division:  Engineering and Applied Science 
Major Option:  Computer Science 
Thesis Availability:  Public (worldwide access) 
Research Advisor(s): 

Thesis Committee: 

Defense Date:  28 May 2002 
Record Number:  CaltechTHESIS:03022011131111881 
Persistent URL:  https://resolver.caltech.edu/CaltechTHESIS:03022011131111881 
Default Usage Policy:  No commercial reproduction, distribution, display or performance rights in this work are provided. 
ID Code:  6263 
Collection:  CaltechTHESIS 
Deposited By:  John Wade 
Deposited On:  03 Mar 2011 17:07 
Last Modified:  02 Dec 2020 02:52 
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