Citation
Nyström, Mika (2001) Asynchronous pulse logic. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechTHESIS:10152010-145548970
Abstract
This thesis explores a new way of computing with CMOS digital circuits, single-track—handshake asynchronous pulse-logic (STAPL). These circuits are similar to quasi delay-insensitive (QDI) circuits, but the normal four-phase QDI handshake is replaced with a simpler two-phase pulsed handshake. While a delay-insensitive two-phase handshake requires complicated decoding circuits, the pulsed handshake maintains the simpler, electrically beneficial signaling senses of four-phase handshaking by using timing assumptions that are easy to meet. We cover many aspects of designing moderately large digital systems out of STAPL circuits, from the communicating-process level to the production-rule and transistor level. We study the theory of operation of pulsed asynchronous circuits, starting with simple pulse repeaters; hence we progress to a general theory of operation for pulsed asynchronous circuits. This theory is a generalization of the theory of operation of synchronous digital circuits. We then develop the family of STAPL circuits. This is a complete family of dataflow processes: the presented circuits can compute unconditionally as well as conditionally; they can also store state and arbitrate. Next, we present some aspects of automatic design-tools for compiling from a higher-level description to STAPL circuits. Many of these aspects apply equally well to tools for QDI circuits; in particular, we study boolean-simplification operations that may be used for improving the performance of slack-elastic asynchronous systems. Finally, a simple 32-bit microprocessor is presented as a demonstration that the circuits and design methods work as described. Comparisons are made, mainly with QDI asynchronous design-styles: SPICE simulations in 0.6-µm CMOS suggest that a system built out of automatically compiled STAPL circuits performs at about three times higher throughput (650-700 MHz in 0.6-µm CMOS) compared with a similar system built out of carefully hand-compiled QDI circuits; the STAPL system uses about twice the energy per operation and twice the area; in other words, the STAPL system improves on the QDI system by four to five times as measured by the Et^2 and At^2 metrics.
| Item Type: | Thesis (Dissertation (Ph.D.)) |
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| Subject Keywords: | Computer Science |
| Degree Grantor: | California Institute of Technology |
| Division: | Engineering and Applied Science |
| Major Option: | Computer Science |
| Thesis Availability: | Restricted to Caltech community only |
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| Thesis Committee: |
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| Defense Date: | 14 May 2001 |
| Record Number: | CaltechTHESIS:10152010-145548970 |
| Persistent URL: | http://resolver.caltech.edu/CaltechTHESIS:10152010-145548970 |
| Default Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. |
| ID Code: | 6147 |
| Collection: | CaltechTHESIS |
| Deposited By: | Benjamin Perez |
| Deposited On: | 16 Oct 2010 02:44 |
| Last Modified: | 26 Dec 2012 04:31 |
Thesis Files
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