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A charge-controlled model for MOS transistors

Citation

Maher, Mary Ann (1989) A charge-controlled model for MOS transistors. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-02082007-135328

Abstract

As MOS (metal-oxide-semiconductor) devices scale to submicron lengths, short-channel effects begin to dominate device behavior, and designers of VLSI (very-large-scale-integrated) circuits see an improved transistor model as a necessary tool. A new physically based, charge-controlled model for the DC current, the intrinsic terminal charges, and the transcapacitances in the MOS transistor under quasistatic conditions has been developed. The model expresses the current in the MOS transistor in terms of the mobile charge per unit area in the channel, and uses a complete set of natural units for velocity, voltage, length, charge, and current. The current-flow equation for the transistor includes both a drift term and a diffusion term, so that the formulation applies equally over the subthreshold, saturation, and "ohmic" regions of transistor operation and includes the effect of velocity saturation. The solution of this dimensionless current-flow equation using these units is a simple, continuous expression, and is suitable for the computer simulation of integrated circuits. The expression allows the regimes of transistor operation and the behavior of long-channel devices versus short-channel devices to be discerned easily. In particular, the expressions for source and drain terminal charges combine the mobile charge in the channel at the source and drain ends in simple polynomials. Analysis of the model shows a fundamental relation between the transistor transcapacitances and transconductances, and permits the development of efficient simulation models of them. Our physically based transistor model uses parameters derived from the fabrication process by direct measurement and from the dimensions of the device. The zero-order model agrees closely with measurements on the scaling of current with channel length down to submicron channel lengths. For more detailed analog simulations, the model contains several first-order effects calculated as perturbations on the simple model. Comparisons among calculated and measured curves of conductance, capacitance, and drain currents demonstrate the accuracy of the model both above and below threshold for a number of experimental devices of different channel lengths. Results from the model concur with measurements on short-channel transistors down to 0.6-micron channel length. Several analog circuit simulators now contain the mode

Item Type:Thesis (Dissertation (Ph.D.))
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Mead, Carver
Thesis Committee:
  • Unknown, Unknown
Defense Date:30 May 1989
Record Number:CaltechETD:etd-02082007-135328
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-02082007-135328
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:556
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:02 Mar 2007
Last Modified:09 Sep 2013 18:50

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