CaltechTHESIS
  A Caltech Library Service

Soft-error tolerant quasi delay-insensitive circuits

Citation

Jang, Wonjin (2008) Soft-error tolerant quasi delay-insensitive circuits. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-11092007-180524

Abstract

Soft errors deposit sufficient charges on the nodes of a circuit to flip the logic states without causing any physical damage to the circuit. They result in transient, inconsistent corruption of data. One of the main causes of soft errors is alpha particles from IC ackages. A positively charged alpha particle from radioactive decay travels through a circuit and disturbs the distribution of electrons. If the disturbance is large enough, the logical value of a node can change accidentally. In addition to alpha particles from the package, other types of radiation such as cosmic rays from space can also cause soft errors. Other than the radiation effects, soft errors can also be caused by random noise such as inductive or capacitive crosstalk, power supply noise, charge sharing, leakage noise, and so on. The soft-error tolerance of logic circuits has recently been received more attention, since the soft-error rate of advanced CMOS devices is higher than before. For the past three decades, dense memories including DRAM and SRAM, have been known to be more susceptible to soft errors than logic circuits. But it is anticipated that soft-error rate for logic circuits will increase by nine orders of magnitude from 1992 to 2011, at which time it will be comparable to the soft-error rate for unprotected memory elements. As a response to the concern on soft errors, we propose a new method for making asynchronous circuits tolerant to soft errors. The method is different from what is done in synchronous circuits with triple modular redundancy, because it relies on a property unique to asynchronous circuits called `stability.' Stability guarantees that when the binary output of a gate switches, the condition on the input of the gate that caused the transition will remain valid (`stable') until the transition on the output has propagated to the rest of the system. Hence, if we can simply detect that an error has occurred on the output node, and prevent it from propagating to the rest of the system, the persistence of the input condition will restore the proper output. Asynchronous circuits have been attractive to the designers of reliable systems because of their clock-less design, which makes them more robust to variations on computation time of modules. The quasi delay-insensitive~(QDI) design style is one of the most robust asynchronous design styles for general computation; it makes one minimal assumption on delays in gates and wires. QDI circuits are easy to verify, simple, and modular, because the correct operation of a QDI circuit is independent of delays in gates and wires. The recent design of a sub-nanojoule microprocessor has demonstrated that QDI circuits can be energy efficient because only active parts of the system will draw power, and the energy consumed by the clock is saved. Furthermore, a system of QDI circuits can adapt itself to variations of physical parameters such as supply voltage, temperature, doping, and so on. While the effect of the variations on synchronous circuits can be severe, QDI circuits are more robust to the variations. These features make QDI circuits attractive to the designers of a low-power and reliable system, which has become more important as technology scaling advances. First we shall give an overview of how to design a QDI circuit, and what will happen if a soft error occurs on a QDI circuit. Then the crucial components of the method are shown: (1) a special kind of duplication for random logic (when each bit has to be corrected individually), (2) special protection circuitry for arbiter and synchronizer (as needed for example for external interrupts), (3) reconfigurable circuits using a special configuration unit, and (4) error correcting for memory arrays and other structures in which the data bits can be self-corrected. The solution of protecting random logic is compared with alternatives, which use other types of error correcting codes (e.g., parity code) in a QDI circuit. It turns out that the duplication generates efficient circuits more commonly than other possible constructions. Finally, the design of a soft-error tolerant asynchronous microprocessor~(STAM) is detailed and testing results of the soft-error tolerance of the STAM are shown.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:asynchronous circuits; QDI; soft error; error tole
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Martin, Alain J.
Thesis Committee:
  • Martin, Alain J. (chair)
  • Bruck, Jehoshua
  • Chandy, K. Mani
  • Ho, Tracey C.
  • Abu-Mostafa, Yaser S.
Defense Date:11 September 2007
Record Number:CaltechETD:etd-11092007-180524
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-11092007-180524
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:5260
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:05 Dec 2007
Last Modified:26 Dec 2012 03:17

Thesis Files

[img]
Preview
PDF (main.pdf) - Final Version
See Usage Policy.

2815Kb

Repository Staff Only: item control page