Salam, Gamze Erten (1994) An analog VLSI architecture for stereo correspondence. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-12072007-084843
My goal in engaging in this project was to design a hardware system to solve the stereo correspondence problem in real-time.
Consequently, this work describes and analyzes an algorithm for stereo correspondence, its extension to an analog VLSI architecture, and the results obtained from its hardware implementation as a chip.
The first chapter, titled Introduction, describes the stereo correspondence problem. Therein, I discuss biological and psychophysical mechanisms of stereo vision, and include a brief history of ideas to date on the subject. I wrote this chapter to introduce the problem to the reader without assuming any previous knowledge about vision. I believe that reading it with the aid of definitions in the glossary can equip most any reader with information regarding the basics of stereo vision.
The second chapter, titled In Search of the Correct Similarity Measure, expands, first by a simple example, later in mathematical terms, the issues involved in the selection of a similarity measure. The similarity measure is a key component in the solution of the stereo correspondence problem. My main approach is a statistical one, using probability distributions and Bayesian analysis. The chapter motivates the two-sided approach of the algorithm, by using a disparity and a confidence metric for each image region.
The third chapter, titled Simulating the Hardware Algorithm, describes my stereo correspondance algorithm in detail. Simulation results that include both disparity and confidence values obtained with a variety of images are presented. Experiments are conducted to demonstrate the effect of parameter adjustments. In addition, the algorithm is compared with other correspondence schemes which use various different similarity measures.
The fourth chapter, titled Analog VLSI Implementation, is devoted fully to the hardware implementation. First, the details of the hardware architecture are described. Then, results are presented with two unique implementations. As in the previous chapter, experiments are conducted, this time using the chips themselves. Their results are compared with simulation. Again a variety of images are used.
The fifth chapter, titled Conclusions and Future Work, summarizes the work and explores future expansions.
|Item Type:||Thesis (Dissertation (Ph.D.))|
|Degree Grantor:||California Institute of Technology|
|Division:||Engineering and Applied Science|
|Major Option:||Electrical Engineering|
|Thesis Availability:||Restricted to Caltech community only|
|Defense Date:||24 August 1993|
|Default Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Imported from ETD-db|
|Deposited On:||14 Dec 2007|
|Last Modified:||26 Dec 2012 03:12|
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