Citation
DeBenedictis, Erik P. (1982) Techniques for testing integrated circuits. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-09062006-111645
Abstract
A language is presented for describing tests of integrated circuits. The language has a high abstractive capability that enables test specifications to follow the structural or logical organization of a design. The test language is applied to a number of current design styles in a series of examples. Methods for designing integrated circuits for testability are demonstrated. An implementation of the test language through a test language interpreter and a tester is discussed. Tester designs are presented that will execute the test language with unusually high efficiency.
| Item Type: | Thesis (Dissertation (Ph.D.)) |
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| Degree Grantor: | California Institute of Technology |
| Division: | Engineering and Applied Science |
| Major Option: | Computer Science |
| Thesis Availability: | Public (worldwide access) |
| Research Advisor(s): |
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| Thesis Committee: |
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| Defense Date: | 5 May 1982 |
| Record Number: | CaltechETD:etd-09062006-111645 |
| Persistent URL: | http://resolver.caltech.edu/CaltechETD:etd-09062006-111645 |
| Default Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. |
| ID Code: | 3358 |
| Collection: | CaltechTHESIS |
| Deposited By: | Imported from ETD-db |
| Deposited On: | 22 Sep 2006 |
| Last Modified: | 26 Dec 2012 02:59 |
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