CaltechTHESIS
  A Caltech Library Service

Testing delay-insensitive circuits

Citation

Hazewindus, Pieter Johannes (1992) Testing delay-insensitive circuits. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-07202007-132706

Abstract

A method is developed to test delay-insensitive circuits, using the single stuck-at fault model. These circuits are synthesized from a high-level specification. Since the circuits are hazard-free by construction, there is no test for hazards in the circuit. Most faults cause the circuit to halt during test, since they cause an acknowledgement not to occur when it should. There are stuck-at faults that do not cause the circuit to halt under any condition. These are stimulating faults; they cause a premature firing of a production rule. For such a stimulating fault to be testable, the premature firing has to be propagated to a primary output. If this is not guaranteed to occur, then one or more test points have to be added to the circuit. Any stuck-at fault is testable, with the possible addition of test points. For combinational delay-insensitive circuits, finding test vectors is reduced to the same problem as for synchronous combinational logic. For sequential circuits, the synthesis method is used to find a test for each fault efficiently, to find the location of the test points, and to find a test that detects all faults in a circuit.

The number of test points needed to fully test the circuit is very low, and the size of the additional testing circuitry is small. A test derived with a simple transformation of the handshaking expansion yields high fault coverage. Adding tests for the remaining faults results in a small complete test for the circuit.

Item Type:Thesis (Dissertation (Ph.D.))
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Restricted to Caltech community only
Research Advisor(s):
  • Martin, Alain J.
Thesis Committee:
  • Martin, Alain J. (chair)
  • Seitz, Charles L.
  • Van de Snepscheut, Jan L. A.
  • Abu-Mostafa, Yaser S.
Defense Date:20 May 1992
Record Number:CaltechETD:etd-07202007-132706
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-07202007-132706
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:2955
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:20 Jul 2007
Last Modified:26 Dec 2012 02:55

Thesis Files

[img] PDF (Hazewindus_pj_1992.pdf) - Final Version
Restricted to Caltech community only
See Usage Policy.

6Mb

Repository Staff Only: item control page