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Performance analysis and optimization of asynchronous circuits


Burns, Steven Morgan (1991) Performance analysis and optimization of asynchronous circuits. Dissertation (Ph.D.), California Institute of Technology.


Analytical techniques are developed to determine the performance of asynchronous digital circuits. These techniques can be used to guide the designer during the synthesis of such a circuit, leading to a high-performance, efficient implementation. Optimization techniques are also developed that further improve this implementation by determining the optimal sizes of the low-level devices (CMOS transistors) that compose the circuit.

Item Type:Thesis (Dissertation (Ph.D.))
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Restricted to Caltech community only
Research Advisor(s):
  • Martin, Alain J.
Thesis Committee:
  • Martin, Alain J. (chair)
  • Seitz, Charles L.
  • Van de Snepscheut, Jan L. A.
  • Franklin, Joel N.
  • Chandy, K. Mani
Defense Date:5 December 1990
Record Number:CaltechETD:etd-07092007-072640
Persistent URL:
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:2835
Deposited By: Imported from ETD-db
Deposited On:23 Jul 2007
Last Modified:26 Dec 2012 02:54

Thesis Files

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