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Millimeter-wave phased arrays in silicon

Citation

Natarajan, Arun Sridhar (2007) Millimeter-wave phased arrays in silicon. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-06012007-130844

Abstract

Integration of mm-wave multiple-antenna systems on silicon-based processes enables complex, low-cost systems for high-frequency communication and sensing applications. While individual silicon devices struggle to achieve the same performance as III-V semiconductor-based transistors at mm-wave frequencies, the benefits of integration, such as good component matching and near-zero incremental device cost, can be leveraged to achieve good system performance. This dissertation presents different techniques and architectures for integrating mm-wave phased arrays on commercial silicon process technologies by demonstrating phased-array transmitters and receivers at 24GHz, 60GHz, and 77GHz, in CMOS and SiGe BiCMOS processes.

Initially, the tradeoffs of high-frequency systems are discussed in the context of Shannon capacity and the benefits of integrating phased arrays at such high frequencies are discussed in detail. An analysis of the output noise in a phased-array receiver in the presence of antenna coupling and input noise correlation is carried out and measurements on a discrete two-element array demonstrate the dependence of output noise on the phase-shift setting.

The design of the first fully-integrated 24GHz phased-array transmitter using mainly 0.18[mu]m CMOS transistors is described. The four-element array adopts a centralized LO-path phase-shifting approach using a multi-phase VCO. The on-chip 19.2GHz VCO generates 16 equally spaced LO phases leading to 7 degree beam resolution for radiation normal to the array. The transmitter includes four on-chip CMOS power amplifiers, with outputs matched to 50 Ohms, that are each capable of generating up to 14.5dBm of output power at 24GHz. The array achieves a peak-to-null ratio of 23dB with four elements active and can support data rates of 500Mb/s on each channel (with BPSK modulation) while occupying 6.8mm x 2.1mm of die area.

A high-resolution local LO-path phase-shifting architecture is presented as part of the first fully-integrated 77GHz phased-array transceiver in a SiGe BiCMOS process. The SiGe transceiver includes four transmit and four receive elements (including 77GHz LNA and PA), along with the LO frequency generation and distribution circuitry. The local LO-path phase-shifting scheme enables a robust distribution network that scales well with increasing frequency and/or number of elements, while providing high-resolution phase shifts. Each transmit element of the heterodyne transmitter generates +12.5dBm of output power at 77GHz, with a bandwidth of 2.5GHz leading to a four-element EIRP of 24.5dBm. Each on-chip PA has a maximum saturated power of +17.5dBm at 77GHz while the on-chip VCO achieves a phase noise of -95dBc/Hz@1MHz offset at 54GHz. The phased-array performance is measured using an internal test option and achieves 12dB peak-to-null ratio with two transmit and receive elements active.

While the 24GHz and 77GHz array are multiple-input single-output systems, higher-order phase-shifting and combining techniques can be used to achieve arrays with multiple outputs, with beams focused on different directions concurrently. Toward this end, a 60GHz bidirectional RF-combined phased array front-end is implemented in SiGe BiCMOS, using a hybrid parallel/series phase-shift approach that reduces the requirements of the on-chip phase shifters, enabling RF signal combining. The four-element array enables simultaneous illumination of two angles of incidence and includes amplitude control, as well as continuous phase adjustment. The front-end has a noise figure lower than 6.9dB at 60GHz and the array achieves full spatial coverage with peak-to-null ratio higher than 25dB. The four-element front-end consumes 265mW and occupies 4.6mm2 of die area.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:CMOS phased arrays; LO-path phase shifting; mm-wave integrated circuits; Multibeam arrays; output noise in phased arrays; phased arrays; SiGe phased arrays
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Electrical Engineering
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Hajimiri, Ali
Thesis Committee:
  • Hajimiri, Ali (chair)
  • Yang, Changhuei
  • Rutledge, David B.
  • D'Addario, Larry R.
  • Weinreb, Sander
Defense Date:17 May 2007
Record Number:CaltechETD:etd-06012007-130844
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-06012007-130844
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:2367
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:04 Jun 2007
Last Modified:26 Dec 2012 02:50

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