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Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

Citation

Wu, Hui (2003) Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-05302003-160130

Abstract

High-frequency/high-speed integrated circuits become increasingly important because of the strong demand for higher data rate and lower power consumption, and they rely more on silicon-based technologies, which has the advantages of low cost, fast technological development and system-on-a-chip (SoC) capabilities. However, silicon technologies also present great challenges in high-frequency/high-speed integrated circuits. This work demonstrated that distributed circuit and injection locking are two enabling circuit techniques that can help overcome silicon limitations. Distributed voltage-controlled oscillators (DVCO's) demonstrated the high-frequency capabilities of distributed circuits. The operation of distributed oscillators is analyzed and the general oscillation condition is derived, resulting in analytical expressions for the oscillation frequency and amplitude. Two tuning techniques are developed, namely, the inherent-varactor tuning and delay-balanced current-steering tuning. A complete analysis of the tuning techniques is also presented. CMOS and bipolar DVCO prototypes have been designed and fabricated in a commercial $0.35{mu}m$ {BiCMOS} process. A 10-GHz CMOS DVCO achieves a tuning range of 12\% and a phase noise of -103~dBc/Hz at 600~kHz frequency offset. A 12-GHz bipolar DVCO achieves a tuning range of 26\% and a phase noise of -99~dBc/Hz at 600~kHz frequency offset. New DVCO architectures are also proposed to improve the performance. The distributed circuit technique is also used for equalization in high-speed fiber-optic systems, in which inter-symbol interference (ISI) caused by fibre dispersion imposes a major limitation. Compared to optical-domain methods and other electrical-domain methods, equalization with distributed transversal filters (DTF's) presents the most cost-effective and SoC-compatible solution. Prototype DTF's have been implemented in a commercial $0.18{mu}m$ {SiGe BiCMOS} process for 10~Gpbs fiber-optic systems. A 7-tap DTF reduces the ISI of a 10~Gbps signal after 800m $50{mu}m$ multi-mode fiber from 5~dB to 1.38~dB, and improves the BER from $10^{-5}$ to $10^{-12}$. The injection locking technique is applied in high-speed, low-power frequency dividers, namely, injection-locked frequency dividers (ILFD's). Based on the detailed analysis, shunt-peaking and oscillation-suppression techniques are developed to enhance the locking range. Prototypes are implemented in a commercial $0.35{mu}m$ {BiCMOS} process using only CMOS transistors. A 19~GHz ILFD achieves a locking range of 1350~MHz with the power consumption of 1~mW. A 9~GHz ILFD achieves a locking range of 1490~MHz with the power consumption of 1.3~mW. Self-dividing oscillators are proposed to generate accurate low-phase-noise quadrature signals.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:distributed circuit; high frequency; high speed; injection locking; integrated circuits; radio-frequency
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Electrical Engineering
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Hajimiri, Ali
Thesis Committee:
  • Hajimiri, Ali (chair)
  • Rutledge, David B.
  • Weinreb, Sander
  • Bridges, William B.
  • Tai, Yu-Chong
Defense Date:11 September 2002
Record Number:CaltechETD:etd-05302003-160130
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-05302003-160130
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:2296
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:04 Jun 2003
Last Modified:10 Dec 2014 19:57

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