Naeimi, Helia (2005) A greedy algorithm for tolerating defective crosspoints in nanoPLA design. Master's thesis, California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-05052005-164226
Recent developments suggest both plausible fabrication techniques and viable architectures for building sublithographic Programmable Logic Arrays using molecular-scale wires and switches. Designs at this scale will see much higher defect rates than in conventional lithography. However, these defects need not be an impediment to programmable logic design at this scale.
We introduce a strategy for tolerating defective crosspoints in PLA architecture. We develop a linear-time, greedy algorithm for mapping PLA logic around crosspoint defects. The mapping algorithm matches the PLA logic to the defect configuration of each device.
We note that P-term fanin must be bounded to guarantee low overhead mapping and develop analytical guidelines for bounding fanin. We further quantify analytical and empirical mapping overhead rates. Including fanin bounding, our greedy mapping algorithm maps a large set of benchmark designs with 13% average overhead for random junction defect rates as high as 20%.
|Item Type:||Thesis (Master's thesis)|
|Subject Keywords:||defect tolerant; molecular electronic; nanoscale design|
|Degree Grantor:||California Institute of Technology|
|Division:||Engineering and Applied Science|
|Major Option:||Computer Science|
|Thesis Availability:||Public (worldwide access)|
|Defense Date:||20 March 2005|
|Non-Caltech Author Email:||helia (AT) caltech.edu|
|Default Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Imported from ETD-db|
|Deposited On:||13 May 2005|
|Last Modified:||26 Dec 2012 02:40|
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