Browse by Committee Member

D

DeLorimier, Michael John (2013) GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/M3TW-7Y53. https://resolver.caltech.edu/CaltechTHESIS:08192012-145253489

F

Fan, Chenggong Charles (2001) Fault-tolerant cluster of networking elements. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/R15B-VD58. https://resolver.caltech.edu/CaltechETD:etd-08152001-144501

K

Kapre, Nachiket Ganesh (2011) SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/QVZR-VB52. https://resolver.caltech.edu/CaltechTHESIS:10262010-082537998

M

Mehta, Nikil (2013) An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/358S-CW22. https://resolver.caltech.edu/CaltechTHESIS:10072012-230900231

N

Naeimi, Helia (2008) Reliable Integration of Terascale Systems with Nanoscale Devices. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/P842-7B49. https://resolver.caltech.edu/CaltechETD:etd-01242008-012650

Nyström, Mika (2001) Asynchronous Pulse Logic. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/B107-MW15. https://resolver.caltech.edu/CaltechTHESIS:10152010-145548970

P

Prakash, Piyush (2008) Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/9HMY-RR92. https://resolver.caltech.edu/CaltechETD:etd-05262008-234258

Papadantonakis, Karl Spyros (2006) Rigorous Analog Verification of Asynchronous Circuits. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/4R8F-WF03. https://resolver.caltech.edu/CaltechETD:etd-01132006-152609

Pénzes, Paul Ivan (2002) Energy-Delay Complexity of Asynchronous Circuits. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/9jpj-5s67. https://resolver.caltech.edu/CaltechTHESIS:03022011-131111881

W

Wong, Catherine Grace (2004) High-Level Synthesis and Rapid Prototyping of Asynchronous VLSI Systems. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/5N2N-0W58. https://resolver.caltech.edu/CaltechTHESIS:11192009-161338958