Citation
Chang, Xiaofei (2014) Resetting Asynchronous QDI Systems. Master's thesis, California Institute of Technology. doi:10.7907/RNGK-RV18. https://resolver.caltech.edu/CaltechTHESIS:10042013-160844239
Abstract
Quasi Delay-Insensitive (QDI) systems must be reset into a valid initial state before normal operation can start. Otherwise, deadlock may occur due to wrong handshake communication between processes. This thesis first reviews the traditional Global Reset Schemes (GRS). It then proposes a new Wave Reset Schemes (WRS). By utilizing the third possible value of QDI data codes - reset value, WRS propagates the data with reset value and triggers Local Reset (LR) sequentially. The global reset network for GRS can be removed and all reset signals are generated locally for each process. Circuits templates as well as some special blocks are modified to accommodate the reset value in WRS. An algorithm is proposed to choose the proper Local Reset Input (LRI) in order to shorten reset time. WRS is then applied to an iterative multiplier. The multiplier is proved working under different operating conditions.
Item Type: | Thesis (Master's thesis) |
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Subject Keywords: | Digital Circuit Design, Asynchronous Systems, QDI Systems, Reset |
Degree Grantor: | California Institute of Technology |
Division: | Engineering and Applied Science |
Major Option: | Computer Science |
Thesis Availability: | Public (worldwide access) |
Research Advisor(s): |
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Thesis Committee: |
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Defense Date: | 30 September 2013 |
Record Number: | CaltechTHESIS:10042013-160844239 |
Persistent URL: | https://resolver.caltech.edu/CaltechTHESIS:10042013-160844239 |
DOI: | 10.7907/RNGK-RV18 |
Default Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. |
ID Code: | 7968 |
Collection: | CaltechTHESIS |
Deposited By: | Xiaofei Chang |
Deposited On: | 09 Oct 2013 16:39 |
Last Modified: | 04 Oct 2019 00:02 |
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