A Caltech Library Service

A fault tolerant integrated circuit memory


Barton, Anthony Francis (1980) A fault tolerant integrated circuit memory. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/dr7k-qn11.


Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity.

A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufacturing defects. The results of the analysis indicate that substantial yield improvement is possible with relatively modest increases in circuit area. Also, the architecture makes it possible to build larger memory circuits than is economically feasible without redundancy.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:Computer Science
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Seitz, Charles L.
Thesis Committee:
  • Unknown, Unknown
Defense Date:14 April 1980
Funding AgencyGrant Number
Record Number:CaltechTHESIS:03212012-110600634
Persistent URL:
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:6861
Deposited By: Benjamin Perez
Deposited On:22 Mar 2012 16:19
Last Modified:09 Nov 2022 19:20

Thesis Files

PDF - Final Version
See Usage Policy.


Repository Staff Only: item control page