Precision Frequency and Phase Synthesis Techniques in Integrated Circuits for Biosensing, Communication and Radar

Citation

Wang, Hua (2009) Precision Frequency and Phase Synthesis Techniques in Integrated Circuits for Biosensing, Communication and Radar. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/T4EC-TX97. https://resolver.caltech.edu/CaltechETD:etd-06102009-164232

Abstract

Today’s CMOS technology provides circuit designers with a powerful implementation platform that supports innovation opportunities on both circuit-topology and system-architecture levels. Moreover, the versatility of CMOS implementation opens the door for a plethora of challenging and exciting interdisciplinary research.

This dissertation focuses on investigating novel techniques and applications for precision frequency and phase synthesis in CMOS. It consists of two parts: a CMOS compatible molecular-level biosensor and a multiple-beam/multi-band scalable CMOS phased array receiver system.

In the first part, a frequency shift based magnetic biosensing scheme is introduced to address the Point-of-Care (PoC) biomolecular diagnosis for high-sensitivity, portable and cost low applications. Compared with existing biosensing schemes, the proposed scheme achieves a competitive sensitivity without using optical devices, external biasing fields or expensive post-processing steps. A discrete implementation first verifies the sensing mechanism and reveals several design insights. An integrated implementation based on standard 130nm CMOS process is then designed with differential sensing and temperature controlling schemes. Overall, with a differential uncertainty of 0.13ppm for relative frequency shift, the sensor achieves reliable detection of one single micron-size magnetic particle (D=4.5um, 2.4um and 1um) as well as 1n-Molar real DNA samples labeled by magnetic nanoparticles (D=50nm).

In the second part, a high-resolution compensation technique is proposed to address mismatch and offset issues encountered by practical phased array system. It employs a dense Cartesian interpolation scheme with an easily scalable architecture and a wide operation bandwidth. As an implementation example, a 6-to-18GHz dual-band quad-beam phased array CMOS receiver is presented, which is capable of forming four spatially independent beams at two different frequencies across the tritave bandwidth. With the mismatch compensation, the array element has achieved a maximum RMS phase error of 0.5˚ with an RMS amplitude variation less than 1.5dB for the 360˚ interpolation over the full operation bandwidth. For a 4-element phased array receiver system based on the designed CMOS chip, the electrical array pattern is measured at 6GHz, 10.4GHz and 18GHz, with the worst case peak-to-null ratio of 21.5dB. In addition, a broadband inductorless design methodology based on Cherry-Hooper topology is proposed for chip area saving. As implementation examples, we will show a DC-19GHz 10dB gain broadband buffer amplifier, a DC-12GHz broadband phase rotator with 10-bit resolution and a beam-forming network in a 10.4GHz to 18GHz phased array receiver chip with dual-beam capability.

Thesis Files