Analog VLSI supervised learning system

Citation

Benson, Ronald Gary (1994) Analog VLSI supervised learning system. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/AFDJ-7S31. https://resolver.caltech.edu/CaltechETD:etd-06152004-095124

Abstract

NOTE: Text or symbols not renderable in plain ASCII are indicated bt [...]. Abstract is included in .pdf document. I built an analog very large-scale integration (VLSI) chip that learns in real-time. I have designed and tested this network in a 2 [...] complementary metal-oxide-silicon (CMOS) process. The chip was fabricated through the Metal-Oxide-Silicon Implementation Service (MOSIS). This fabricated chip contains 12 neurons, each fully connected to the other 11 neurons, but with no self-feedback connection.

The goal of this research is to build a supervised-learning neural-network VLSI chip. This neural chip could reside at a remote site unattended by a microcontroller, be battery operated, and be able to adapt autonomously to a changing environment. The neural chip has connection weights (or synapses) which are analog nonvolatile memories programmed in the presence of ultra-violet light. The chip consumes ultra-low power (less than one nW per synapse). Several other features of the chip distinguish it from previous work: the feedforward nonlinear mapping proceeds concurrently with the training process in real time; the weight modifications are performed in parallel and are calculated collectively as part of the network.

I have successfully trained this chip to perform various mappings. The test mappings performed by the chip have two inputs and one output with four hidden units recruited by the network. The chip is presented with inputs and target outputs and proceeds to learn the mapping from input space to output space. Additional memory on the chip allows any or all of the input units to be enabled: similarly, the neurons can be configured as output units or hidden units. The weights, teaching signals, neuron outputs, error units, inputs, and target outputs can all be displayed on a multisync monitor to aid in debugging while the chip is being trained or run in feedforward mode. I show data of the chip learning.

Thesis Files