Holistic Design in High-Speed Silicon Photonics and Low-Power Electronics Platforms

Citation

Hashemi Talkhooncheh, Arian (2023) Holistic Design in High-Speed Silicon Photonics and Low-Power Electronics Platforms. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/8yj9-2a62. https://resolver.caltech.edu/CaltechTHESIS:06122023-184556858

Abstract

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One area of growing importance in optical interconnects is the design and optimization of energy-efficient transmitters with superior power efficiency. Enhancing the electro-optical bandwidth density while keeping the power efficiency optimized, requires improvement in the optical power penalty of photonic integrated circuits. Moreover, co-optimization of electronics and photonics enables a path towards sub-pJ/b transmission efficiency. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an integrated DAC-less PAM-4 transmitter in a multi-micron silicon photonics platform using 2 binary-driven uneven-length SiGe EAMs in an unbalanced MZI is presented. The optical transmitter exhibits 5.5dB ER at 100 Gb/s with 2.1dB SNR improvement compared to single EAMs driven by PAM-4 signals. Also, A DAC-less 200Gb/s QAM-16 transmitter in a multi-micron silicon-photonics platform using 4 binary-driven SiGe EAMs in an unbalanced MZI is presented. The transmitter exhibits bit-error rates of 3×10-4 and 2.8×10-4 for square and hexagonal constellations. Second, a 100Gb/s PAM4 optical transmitter system implemented in a 3D-integrated Silicon Photonics-CMOS platform is presented. The photonics chip includes a push-pull segmented Mach-Zehnder Modulator (MZM) structure using highly capacitive (415fF to 1.1pF), yet optically efficient (VπL= 0.8 V.cm) metal-oxide-silicon capacitor (MOSCAP) phase modulators. Two pairs of U-shaped modulator segments with effective lengths of 170µm and 450µm are driven at 50 Gbaud by a dual-channel 28nm CMOS driver, which is flip-chip bonded to the photonics chip. The driver cores utilize digitally controllable pre-distortion and inductive peaking to achieve sufficient electro-optical bandwidth. The drivers deliver 1.2Vppd swing to modulators using a 0.9V supply and on-chip serializers that generate 50Gb/s data streams. The electronics chip consumes 240mW achieving 2.4pJ/bit energy efficiency. The overall electro-optical bandwidth (EOBW), without any pre-distortion, is increased by approximately 56% and 48% for the 170µm and 450µm segments, respectively, when compared to their EOBW measured by 65GHz 50-Ohm terminated probes. The optical input power to the photonics chip is +10dBm and an erbium-doped fiber amplifier amplifies output signals by 11dB. The 50Gb/s NRZ optical raw eye diagram exhibits 4.3dB extinction ratio (ER) and 1.2dBm of optical modulation amplitude (OMA). The 100Gb/s PAM4 optical raw eye diagram shows 4.3dB ER and 1.4dBm OMA with a transmitter dispersion eye closure quaternary (TDECQ) of 1.53dB after a 5-tap feed-forward-equalization (FFE) filter. The PAM4 TDECQ changes by 53% when the temperature is increased from 30ºC to 90 ºC at the optimum forward bias voltage of 1V. Third, an efficient cold-starting energy harvester system, fabricated in 65nm CMOS is presented. The proposed harvester uses no external electrical components and is compatible with biofuel-cell voltage and power ranges. A power-efficient system architecture is proposed to keep the internal circuitry operating at 0.4V while regulating the output voltage at 1V using switched-capacitor DC-DC converters and a hysteretic controller. A startup enhancement block is presented to facilitate cold startup with any arbitrary input voltage. A real-time on-chip 2D maximum power point tracking with source degradation tracing is also implemented to maintain power efficiency maximized over time. The system performs cold startup with a minimum input voltage of 0.39V and continues its operation if the input voltage degrades to as low as 0.25V. Peak power efficiency of 86% is achieved at 0.39V of input voltage and 1.34μW of output power with 220nW of average power consumption of the chip. The end-to-end power efficiency is kept above 70% for a wide range of loading powers from 1μW to 12μW. The chip is integrated with a pair of lactate biofuel-cell electrodes with 2mm of diameter on a prototype printed circuit board (PCB). Integrated operation of the chip with the electrodes and a lactate solution is demonstrated.

Thesis Files