Chiueh, Tzi-Dar (1989) Pattern classification and associative recall by neural networks. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechTHESIS:11052012-093038170
The first part of this dissertation discusses a new classifier based on a multilayer feed-forward network architecture. The main idea is to map irregularly-distributed prototypes in a classification problem to codewords that are organized in some way. Then the pattern classification problem is transformed into a threshold decoding problem, which is easily solved using simple hard-limiter neurons. At first we propose the new model and introduce two families of good "internal representation" codes. Then some analyses and software simulation concerning the storage capacity of this new model are done. The results show that the new classifier is much better than the classifier based on the Hopfield model in terms of both the storage capacity and the ability to classify correlated prototypes.
A general model for neural network associative memories with a feedback. structure is proposed. Many existing neural network associative memories can be expressed as special cases of this general model. Among these models, there is a class of associative memories, called correlation associative memories, that are capable of storing a large number of memory patterns. If the function used in the evolution equation is monotonically nondecreasing, then a correlation associative memory can be proved to be asymptotically stable in both the synchronous and asynchronous updating modes.
Of these correlation associative memories, one stands out because of its VLSI implementation feasibility and large storage capacity. This memory uses the exponentiation function in its evolution equation; hence it is called exponential correlation associative memory (ECAM). It is further proved that the storage capacity of ECAM scales exponentially with N (the number of components in memory patterns) when N approaches infinity. A programmable ECAM chip is designed, simulated, fabricated, and then tested. The performance of the ECAM chip is shown to be not much worse than that of a computer-simulated ECAM model in terms of error correcting ability (attraction radius). Finally, the speed of the prototype ECAM chip is demonstrated by employing it to do vector quantization on binary images. And it is found that the ECAM chip can process binary images in real time.
|Item Type:||Thesis (Dissertation (Ph.D.))|
|Subject Keywords:||Electrical Engineering|
|Degree Grantor:||California Institute of Technology|
|Division:||Engineering and Applied Science|
|Major Option:||Electrical Engineering|
|Thesis Availability:||Restricted to Caltech community only|
|Defense Date:||24 May 1989|
|Default Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Benjamin Perez|
|Deposited On:||05 Nov 2012 18:12|
|Last Modified:||26 Dec 2012 04:45|
- Final Version
Restricted to Caltech community only
See Usage Policy.
Repository Staff Only: item control page