Ngai, John Y. (1984) The General Interconnect Problem of Integrated Circuits. Master's thesis, California Institute of Technology. http://resolver.caltech.edu/CaltechTHESIS:04132012-084100294
This thesis is concerned with the interconnection problem of custom integrated circuits. It may be broadly defined as the transformation of circuit description represented by the notion of modules together with the circuit connectivity requirements, into wiring patterns which implement the required connectivities. Conventional approaches to its solution are presented. Issues such as partition to placement and routing and various layout optimization tradeoffs are discussed. A detail hierarchical routing model with timing considerations that extends naturally to multiple conducting layer environment is presented. Several of the implications of this extension are also discussed.
The rest of this thesis deals with an experiment with the stepping approach to routing as an alternative to the conventional cellular approach emphasizing simplicity rather than optimization. Algorithms for routing signals and power developed for the stepping router are presented. An implementation of this approach by the author together with some test examples and their results are also described. This thesis concludes with a few suggestions for further research work in this area which the author considers very important from the experience gained during the work on this thesis.
|Item Type:||Thesis (Master's thesis)|
|Subject Keywords:||Computer Science|
|Degree Grantor:||California Institute of Technology|
|Division:||Engineering and Applied Science|
|Major Option:||Computer Science|
|Thesis Availability:||Restricted to Caltech community only|
|Defense Date:||1 May 1984|
|Other Numbering System:|
|Default Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Benjamin Perez|
|Deposited On:||13 Apr 2012 16:02|
|Last Modified:||26 Dec 2012 04:41|
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