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A 16-Bit LSI digital multiplier

Citation

Masumoto, Rodney Tak (1978) A 16-Bit LSI digital multiplier. Engineer's thesis, California Institute of Technology. http://resolver.caltech.edu/CaltechTHESIS:04122012-143452788

Abstract

Multiplication in digital machines is often done sequentially by the processor's arithmetic logic unit. However, this method is very time consuming due to the many sequential shifts and additions required. Implementing this multiplication directly with hardware increases speed, but at added cost. By implementing an interesting multiplication algorithm on an LSI chip, it is possible to achieve high performance with little added cost.

This paper describes a single chip LSI implementation of such a hardware multiplier. This multiplier/accumulator chip performs a fast multiplication of two 16 bit 2's complement words. It was designed and implemented in silicon gate NMOS with depletion loads. By using a multiple hit examination algorithm, the circuitry requirements were significantly less than that of a standard hardware multiplier. Also, by employing carry-save adders and carry lookahead logic, multiplication delay times are competitive with bipolar implementations, but require one-fifth the power.

An on-chip accumulator allows successive products to be summed without tying up the external data bus. Special completion sensing logic allows the chip to be used in asynchronous timing applications. The 16 bit by 16 bit multiplier chip measures 180 by 180 mils. All circuits are modular, and chips of arbitrary word size can be generated by changing only two parameter values during the computer aided mask layout generation process.

Item Type:Thesis (Engineer's thesis)
Subject Keywords:Computer Science ; Mutiplication ; Data processing
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Computer Science
Thesis Availability:Restricted to Caltech community only
Research Advisor(s):
  • Mead, Carver
Thesis Committee:
  • Unknown, Unknown
Defense Date:1 January 1978
Other Numbering System:
Other Numbering System NameOther Numbering System ID
Computer Science Technical Report4204:TR:78
Record Number:CaltechTHESIS:04122012-143452788
Persistent URL:http://resolver.caltech.edu/CaltechTHESIS:04122012-143452788
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:6923
Collection:CaltechTHESIS
Deposited By: Benjamin Perez
Deposited On:12 Apr 2012 22:42
Last Modified:26 Dec 2012 04:41

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