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Design and characterization of layered tunnel barriers for nonvolatile memory applications

Citation

Casperson, Julie Diane (2004) Design and characterization of layered tunnel barriers for nonvolatile memory applications. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-05262004-111123

Abstract

The main limitations of floating gate memory devices (Flash memory) are the long program (microsecond) and erase times (millisecond) inherent to the charging of floating gates using Fowler-Nordheim tunneling. An alternative to the integration of homogeneous dielectric tunnel barriers present in standard Flash memory is to use ?layered? tunnel barriers made of high-k heterostructures. This allows for an effective lowering in barrier height under applied bias, resulting in shorter write/erase times while maintaining long retention times.

To assess these types of dielectric structures, tunneling probability simulations were performed using an effective mass-model, allowing us to predict current-voltage (I-V) characteristics and optimize the layered tunnel barrier structure. Based on our results, we correlated dielectric constants and band offsets with respect to silicon in order to help identify possible materials from which to construct these layered barriers. This survey allowed for the determination of promising high-k materials heterostructures: Si3N4 / Al2O3 / Si3N4 / Si3N4 and HfO2 / Al2O3 / HfO2.

We performed a series of physical and electrical characterization experiments on single-layer as well as two- and three-layer structures of Si3N4, Al2O3, and HfO2. Transmission electron microscopy and I-V measurements were used to correlate the physical effects of high-temperature annealing on the electrical properties of the films, allowing us to determine the ideal processing conditions. Construction of Fowler-Nordheim plots from experimental I-V data gave qualitative evidence of barrier lowering in the multi-layer structures.

We developed a bias-dependent photoemission technique for quantitative determination of the band-offsets between silicon and our dielectric barriers, which is found to be highly dependent on the applied bias. For SiO2 (and other single-layer materials), image potential barrier lowering simulations predict the barrier profile as a function of voltage, allowing us to report the band-offsets for these materials in a more complete way than was previously possible. Also, by characterizing multi-layer structures of HfO2 and Al2O3, we have been able to quantitatively measure the effective barrier height of these structures over a wide range of biases and prove barrier lowering. Analysis by an electrostatic model allowed us to accurately simulate the barrier lowering results over all voltage ranges.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:ALD; atomic layer deposition; band offset; barrier height; barrier lowering; flash memory; heterostructure; interfacial layer
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Applied Physics
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Atwater, Harry Albert
Thesis Committee:
  • Lewis, Nathan Saul (chair)
  • McKoy, Basil Vincent
  • Atwater, Harry Albert
  • Heath, James R.
Defense Date:17 May 2004
Author Email:jcaspers (AT) caltech.edu
Record Number:CaltechETD:etd-05262004-111123
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-05262004-111123
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:2079
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:26 May 2004
Last Modified:26 Dec 2012 02:46

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