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Monolithic GaAs VLSI optoelectronic neuron arrays

Citation

Luo, Jiafu (1996) Monolithic GaAs VLSI optoelectronic neuron arrays. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-05012006-124513

Abstract

This thesis focuses on the design and fabrication of GaAs monolithic optoelectronic integrated circuits (OEIC's) for use in optical neural networks. The basic circuit in a neuron array consists of GaAs MESFET (Metal-Semiconductor Field Effect Transistor) circuits and optical input/output (I/O) devices. By implementing the I/O process optically, we can greatly increase the neuron density for a 2-dimensional array and thus achieve highly parallel computation. Because of the high loss involved in optical interconnections, high density neuron arrays require high gain photodetectors and high efficiency output devices. With responsivities up to 10(4)A/W and structure compatibility with MESFET circuits, optical FET detectors (OPFET's) are an excellent choice as photodetectors. Several techniques have been investigated in order to fabricate high efficiency LED's (light-emitting-diodes) at low current levels. Low power consumption neurons based on OPFET's and GaAs/A1GaAs double-Zn-diffusion double-heterojunction LED's are fabricated using in-house facilities. Industrial foundries provide the most convenient answer to the challenge of fabricating high density 2-D neuron arrays. Two approaches will be described. The first approach utilizes the FET-SEED (self-electrooptic effect device) process from AT&T Bell labs. It provides monolithically integrated circuits with optical I/O devices and depletion mode FET's. In the other approach, GaAs/AlGaAs multiple quantum well modulators are grown on MOSIS GaAs MESFET circuits by MBE regrowth. It is found that in both approaches, the FET's can be used as high gain photodetectors even though the mechanisms are different, thus making it possible to achieve low power consumption high density neuron arrays. Various kinds of complex optoelectronic circuits can be fabricated through these two approaches.

Item Type:Thesis (Dissertation (Ph.D.))
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Electrical Engineering
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Psaltis, Demetri
Thesis Committee:
  • Psaltis, Demetri (chair)
  • Yariv, Amnon
  • Mead, Carver
  • Nicolet, Marc-Aurele
  • Corngold, Noel Robert
Defense Date:27 September 1995
Author Email:jiafu.luo (AT) esstech.com
Record Number:CaltechETD:etd-05012006-124513
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-05012006-124513
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:1560
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:01 May 2006
Last Modified:26 Dec 2012 02:39

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