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CMOS imaging technology with embedded early image processing

Citation

Basset, Christophe Jean-Michel (2007) CMOS imaging technology with embedded early image processing. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd-04262007-131214

Abstract

As imaging technology evolves, so does the need for accurate, low-power and high-data-rate low-level image processing in a variety of computationally intensive vision applications. These applications include optical-flow computation, autonomous navigation, object avoidance or intercept, real-time target tracking, and recognition. To reach this goal, a single chip was developed, which functions as a camera able to preprocess the image in real time. It processes images through a convolution filter with a user-chosen kernel. One of the particulars of this project is to combine the processing unit with an active pixel sensors (APS) pixel array. This complementary metal-oxide semiconductor (CMOS) technology for building imager chips allows on-focal plane signal processing, as opposed to their charge-coupled device (CCD) counterparts that need to serially output the flow of pixels to an external processing chip. The filtering can therefore be implemented as a fast, low-power analog circuit. Convolution is achieved by matching a kernel to an image using a computation unit. The chip has an integrated imager array and a digital memory large enough to store a generic, up-loadable kernel. When recognizing or tracking a target, the uploaded kernel represents the template. Other convolution filters are implemented by setting the kernel to the set of parameters corresponding to the desired task. Filtering is performed through a column-parallel architecture of computing units, so real time computation can be achieved. Several versions of the convolution circuit are investigated. They have been fabricated, fully tested and characterized. A number of important design changes have occurred, either to address issues that could be improved on or to experiment with alternative approaches. Timed and geometrical amplifier controls have also been investigated. By implementing image arrays of different sizes, we also demonstrate the scalability of the architecture in the spatial domain to an arbitrarily sized imager. Test results show the analog convolution chip is a viable solution for highly integrated embedded early image processing.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:Active Pixel Sensor; Analog circuit; APS; CMOS imager; Convolution; FPGA; Image processing; Mixed-signal; Optical flow; Vision chip
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Electrical Engineering
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Perona, Pietro
Thesis Committee:
  • Perona, Pietro (chair)
  • Hajimiri, Ali
  • Pain, Bedabrata
  • Mathur, Bimal
  • Koch, Christof
  • Martin, Alain J.
Defense Date:6 April 2007
Author Email:basset (AT) vision.caltech.edu
Record Number:CaltechETD:etd-04262007-131214
Persistent URL:http://resolver.caltech.edu/CaltechETD:etd-04262007-131214
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:1516
Collection:CaltechTHESIS
Deposited By: Imported from ETD-db
Deposited On:16 May 2007
Last Modified:26 Dec 2012 02:38

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