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Energy-Efficient Receiver Design for High-Speed Interconnects

Citation

Chen, Kuan-Chang (2022) Energy-Efficient Receiver Design for High-Speed Interconnects. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/ntem-sn47. https://resolver.caltech.edu/CaltechTHESIS:08042021-231915829

Abstract

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise ratio (SNR) of the front-end circuits, or equalization that mitigates the detrimental inter-symbol interference (ISI) is required. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented.

First, an avalanche photodetector (APD)-based optical receiver is described, which utilizes non-return-to-zero (NRZ) modulation and is applicable to burst-mode operation. For the purposes of improving the overall optical link energy efficiency as well as the link bandwidth, this optical receiver is designed to achieve high sensitivity and high reconfiguration speed. The high sensitivity is enabled by optimizing the SNR at the front-end through adjusting the APD responsivity via its reverse bias voltage, along with the incorporation of 2-tap feedforward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion. The high reconfiguration speed is empowered by the proposed integrating dc and amplitude comparators, which eliminate the RC settling time constraints. The receiver circuits, excluding the APD die, are fabricated in 28-nm CMOS technology. The optical receiver achieves bit-error-rate (BER) better than 1E−12 at −16-dBm optical modulation amplitude (OMA), 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s.

Second, a 4-level pulse amplitude modulation (PAM4) wireline receiver is described, which incorporates continuous time linear equalizers (CTLEs) and a 2-tap direct DFE dedicated to the compensation for the first and second post-cursor ISI. The direct DFE in a PAM4 receiver (PAM4-DFE) is made possible by the proposed CMOS track-and-regenerate slicer. This proposed slicer offers rail-to-rail digital feedback signals with significantly improved clock-to-Q delay performance. The reduced slicer delay relaxes the settling time constraint of the summer circuits and allows the stringent DFE timing constraint to be satisfied. With the availability of a direct DFE employing the proposed slicer, inductor-based bandwidth enhancement and loop-unrolling techniques, which can be power/area intensive, are not required. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieves BER better than 1E−12 and 1.1-pJ/b energy efficiency at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist frequency.

Third, digital neural-network-enhanced FFEs (NN-FFEs) for PAM4 analog-to-digital converter (ADC)-based optical interconnects are described. The proposed NN-FFEs employ a custom learnable piecewise linear (PWL) activation function to tackle the nonlinearities with short memory lengths. In contrast to the conventional Volterra equalizers where multipliers are utilized to generate the nonlinear terms, the proposed NN-FFEs leverage the custom PWL activation function for nonlinear operations and reduce the required number of multipliers, thereby improving the area and power efficiencies. Applications in the optical interconnects based on micro-ring modulators (MRMs) are demonstrated with simulation results of 50-Gb/s and 100-Gb/s links adopting PAM4 signaling. The proposed NN-FFEs and the conventional Volterra equalizers are synthesized with the standard-cell libraries in a commercial 28-nm CMOS technology, and their power consumptions and performance are compared. Better than 37% lower power overhead can be achieved by employing the proposed NN-FFEs, in comparison with the Volterra equalizer that leads to similar improvement in the symbol-error-rate (SER) performance.

Item Type:Thesis (Dissertation (Ph.D.))
Subject Keywords:Integrated Circuits; Mixed-Signal Circuit Design; Wireline; Optical; Electrical; Interconnects; CMOS Receiver; Equalization; High-Speed; Energy-Efficient
Degree Grantor:California Institute of Technology
Division:Engineering and Applied Science
Major Option:Electrical Engineering
Thesis Availability:Public (worldwide access)
Research Advisor(s):
  • Emami, Azita
Thesis Committee:
  • Marandi, Alireza (chair)
  • Emami, Azita
  • Scherer, Axel
  • Nelson, David
Defense Date:20 July 2021
Record Number:CaltechTHESIS:08042021-231915829
Persistent URL:https://resolver.caltech.edu/CaltechTHESIS:08042021-231915829
DOI:10.7907/ntem-sn47
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/CICC.2018.8357074DOIConference paper presented at CICC 2018, adapted for Chapter 3
https://doi.org/10.1109/JSSC.2019.2902471DOIJournal paper published in JSSC 2019, adapted for Chapter 3
https://doi.org/10.1109/CICC48029.2020.9075948DOIConference paper presented at CICC 2020, adapted for Chapter 4
https://doi.org/10.1109/JSSC.2020.3025285DOIJournal paper published in JSSC 2021, adapted for Chapter 4
ORCID:
AuthorORCID
Chen, Kuan-Chang0000-0003-2968-4656
Default Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:14318
Collection:CaltechTHESIS
Deposited By: Kuan Chang Chen
Deposited On:19 Aug 2021 21:17
Last Modified:26 Aug 2021 16:20

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